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| GAL26CLV12 Low Voltage E2CMOS PLD Generic Array LogicTM FEATURES Features * HIGH PERFORMANCE E2CMOS(R) TECHNOLOGY -- 5 ns Maximum Propagation Delay -- Fmax = 200 MHz -- 3.5 ns Maximum from Clock Input to Data Output -- UltraMOS(R) Advanced CMOS Technology * 3.3V LOW VOLTAGE 26CV12 ARCHITECTURE -- JEDEC-Compatible 3.3V Interface Standard -- Inputs and I/O Interface with Standard 5V TTL Devices * ACTIVE PULL-UPS ON ALL PINS * E2 CELL TECHNOLOGY -- Reconfigurable Logic -- Reprogrammable Cells -- 100% Tested/100% Yields -- High Speed Electrical Erasure (<100ms) -- 20 Year Data Retention * TWELVE OUTPUT LOGIC MACROCELLS -- Maximum Flexibility for Complex Logic Designs -- Programmable Output Polarity * PRELOAD AND POWER-ON RESET OF ALL REGISTERS -- 100% Functional Testability * APPLICATIONS INCLUDE: -- Glue Logic for 3.3V Systems -- DMA Control -- State Machine Control -- High Speed Graphics Processing -- Standard Logic Speed Upgrade * ELECTRONIC SIGNATURE FOR IDENTIFICATION I Functional Block Diagram I/CLK RESET INPUT 8 I 8 I 8 I 8 I OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q PROGRAMMABLE AND-ARRAY (122X52) OLMC I/O/Q 10 OLMC I/O/Q I 12 OLMC I/O/Q I 12 OLMC I/O/Q I 10 OLMC I/O/Q I 8 I 8 I 8 I 8 OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC PRESET I/O/Q Description The GAL26CLV12D, at 5 ns maximum propagation delay time, provides higher performance than its 5V counterpart. The GAL26CLV12D can interface with both 3.3V and 5V signal levels. The GAL26CLV12D is manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which combines CMOS with Electrically Erasable (E2) floating gate technology. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. Pin Configuration PLCC I/CLK I/O/Q I/O/Q 26 25 I I 2 4 I I I VCC I I I I 5 I 28 I/O/Q I/O/Q I/O/Q I/O/Q GND I/O/Q I/O/Q 7 GAL26CLV12D Top View 23 9 21 11 12 14 16 19 18 I/O/Q I/O/Q I/O/Q Copyright (c) 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. I/O/Q I I I LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com July 1997 26clv12_02 1 Specifications GAL26CLV12 GAL26CLV12D Ordering Information Commercial Grade Specifications Tpd (ns) 5 7.5 Tsu (ns) 3.5 5.5 Tco (ns) 3.5 4.5 Icc (mA) 130 130 Ordering # GAL26CLV12D-5LJ GAL26CLV12D-7LJ Package 28-Lead PLCC 28-Lead PLCC Part Number Description XXXXXXXX _ XX X XX GAL26CLV12D Device Name Grade Blank = Commercial Speed (ns) L = Low Power Power Package J = PLCC 2 Specifications GAL26CLV12 Output Logic Macrocell (OLMC) The GAL26CLV12D has a variable number of product terms per OLMC. Of the twelve available OLMCs, two OLMCs have access to twelve product terms (pins 20 and 22), two have access to ten product terms (pins 19 and 23), and the other eight OLMCs have eight product terms each. In addition to the product terms available for logic, each OLMC has an additional product term dedicated to output enable control. The output polarity of each OLMC can be individually programmed to be true or inverting, in either combinatorial or registered mode. This allows each output to be individually configured as either active high or active low. The GAL26CLV12D has a product term for Asynchronous Reset (AR) and a product term for Synchronous Preset (SP). These two product terms are common to all registered OLMCs. The Asynchronous Reset sets all registered outputs to zero any time this dedicated product term is asserted. The Synchronous Preset sets all registers to a logic one on the rising edge of the next clock pulse after this product term is asserted. NOTE: The AR and SP product terms will force the Q output of the flip-flop into the same state regardless of the polarity of the output. Therefore, a reset operation, which sets the register output to a zero, may result in either a high or low at the output pin, depending on the pin polarity chosen. AR D Q CLK SP Q 4 TO 1 MUX 2 TO 1 MUX GAL26CLV12D OUTPUT LOGIC MACROCELL (OLMC) Output Logic Macrocell Configurations Each of the Macrocells of the GAL26CLV12D has two primary functional modes: registered, and combinatorial I/O. The modes and the output polarity are set by two bits (S0 and S1), which are normally controlled by the logic compiler. Each of these two primary modes, and the bit settings required to enable them, are described below and on the following page. REGISTERED In registered mode the output pin associated with an individual OLMC is driven by the Q output of that OLMC's D-type flip-flop. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an individual product-term for each OLMC, and can therefore be defined by a logic equation. The D flip-flop's /Q output is fed back into the AND array, with both the true and complement of the feedback available as inputs to the AND array. NOTE: In registered mode, the feedback is from the /Q output of the register, and not from the pin; therefore, a pin defined as registered is an output only, and cannot be used for dynamic I/O, as can the combinatorial pins. COMBINATORIAL I/O In combinatorial mode the pin associated with an individual OLMC is driven by the output of the sum term gate. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an individual product-term for each output, and may be individually set by the compiler as either "on" (dedicated output), "off" (dedicated input), or "product-term driven" (dynamic I/O). Feedback into the AND array is from the pin side of the output enable buffer. Both polarities (true and inverted) of the pin are fed back into the AND array. 3 Specifications GAL26CLV12 Registered Mode AR AR D Q D Q CLK SP Q CLK SP Q ACTIVE LOW S0 = 0 S1 = 0 S0 = 1 S1 = 0 ACTIVE HIGH Combinatorial Mode ACTIVE LOW S0 = 0 S1 = 1 S0 = 1 S1 = 1 ACTIVE HIGH 4 Specifications GAL26CLV12 GAL26CLV12D Logic Diagram/JEDEC Fuse Map PLCC Package Pinout 1 0 4 8 12 16 20 24 28 32 36 40 44 48 0000 0052 . . . 0468 ASYNCHRONOUS RESET (TO ALL REGISTERS) 28 8 OLMC S0 6344 S1 6345 27 2 0520 . . . 0936 8 OLMC S0 6346 S1 6347 26 3 0988 . . . 1404 8 OLMC S0 6348 S1 6349 25 4 1456 . . . 1872 8 OLMC S0 6350 S1 6351 24 5 1924 . . . . 2444 10 OLMC S0 6352 S1 6353 23 6 2496 . . . . . 3120 12 OLMC S0 6354 S1 6355 22 8 3172 . . . . . 3796 12 OLMC S0 6356 S1 6357 20 9 3848 . . . . 4368 10 OLMC S0 6358 S1 6359 19 10 4420 . . . 4836 8 OLMC S0 6360 S1 6361 18 11 4888 . . . 5304 8 OLMC S0 6362 S1 6363 17 12 5356 . . . 5772 8 OLMC S0 6364 S1 6365 16 13 5824 . . . 6240 8 OLMC S0 6366 S1 6367 15 14 6292 SYNCHRONOUS PRESET (TO ALL REGISTERS) 6368, 6369 ... M S B L S B Electronic Signature ... 6430, 6431 Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 5 Specifications GAL26CLV12 Absolute Maximum Ratings(1) Supply voltage VCC .................................... -0.5 to +4.6V Input or I/O voltage applied ....................... -0.5 to +5.6V Off-state output voltage applied ................ -0.5 to +4.6V Storage Temperature ................................. -65 to 150C Ambient Temperature with Power Applied ......................................... -55 to 125C 1.Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). Recommended Operating Conditions Commercial Devices: Ambient Temperature (TA) ............................. 0 to +75C Supply voltage (VCC) with Respect to Ground ......................... +3.0 to +3.6V DC Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER Input Low Voltage Input High Voltage I/O High Voltage CONDITION MIN. Vss - 0.3 2.0 2.0 0V VIN VIL (MAX.) (Vcc-0.2)V VIN VCC Vcc VIN 5.25V Vcc VIN 5.25V IOL = MAX. Vin = VIL or VIH IOL = 500A Vin = VIL or VIH -- -- -- -- -- -- 2.4 Vcc-0.2V -- -- VCC = 3.3V VOUT = 0.5V TA= 25C -15 TYP.3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- MAX. 0.8 5.25 Vcc+0.5 -100 10 10 2 0.4 0.2 -- -- 8 -8 -80 UNITS V V V A A A mA V V V V mA mA mA VIL VIH IIL1 IIH Input or I/O Low Leakage Current Input or I/O High Leakage Current Input Leakage Current I/O Leakage Current VOL VOH IOL IOH IOS2 Output Low Voltage Output High Voltage IOH = MAX. Vin = VIL or VIH IOH = -100A Vin = VIL or VIH Low Level Output Current High Level Output Current Output Short Circuit Current COMMERCIAL ICC Operating Power Supply Current VIL = 0V VIH = 3.0V Unused Inputs at GND ftoggle = 15MHz Outputs Open -- 90 130 mA 1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 3.3V and TA = 25 C 6 Specifications GAL26CLV12 AC Switching Characteristics Over Recommended Operating Conditions COM PARAMETER COM TEST COND1. A A -- -- -- A DESCRIPTION Input or I/O to Combinational Output Clock to Output Delay Clock to Feedback Delay Setup Time, Input or Feedback before Clock Hold Time, Input or Feedback after Clock Maximum Clock Frequency with External Feedback, 1/(tsu + tco) Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf) Maximum Clock Frequency with No Feedback Clock Pulse Duration, High Clock Pulse Duration, Low Input or I/O to Output Enabled Input or I/O to Output Disabled Input or I/O to Asynchronous Reset of Register Asynchronous Reset Pulse Duration Asynchronous Reset to Clock Recovery Time Synchronous Preset to Clock Recovery Time 1 1 -- 3.5 0 -5 -7 UNITS MIN. MAX. MIN. MAX. tpd2 tco2 tcf3 tsu th 5 3.5 3 -- -- -- 1 1 -- 5.5 0 100 7.5 4.5 3 -- -- -- ns ns ns ns ns MHz 143 fmax4 A 154 -- 117 -- MHz A 200 -- 142 -- MHz twh4 twl4 ten tdis tar tarw tarr tspr 1) 2) 3) 4) -- -- B C A -- -- -- 2.5 2.5 1 1 1 5.5 4 4 -- -- 6 6 6 -- -- -- 3.5 3.5 1 1 1 7 5 5 -- -- 7.5 7.5 9 -- -- -- ns ns ns ns ns ns ns ns Refer to Switching Test Conditions section. Minimum values for tpd and tco are not 100% tested but established by characterization. Calculated from fmax with internal feedback. Refer to fmax Descriptions section. Refer to fmax Descriptions section. Characterized but not 100% tested. Capacitance (TA = 25C, f = 1.0 MHz) SYMBOL CI CI/O PARAMETER Input Capacitance I/O Capacitance TYPICAL 8 8 UNITS pF pF TEST CONDITIONS VCC = 3.3V, VI = 0V VCC = 3.3V, VI/O = 0V 7 Specifications GAL26CLV12 Switching Waveforms INPUT or I/O FEEDBACK VALID INPUT INPUT or I/O FEEDBACK VALID INPUT tpd COMBINATORIAL OUTPUT ts u CLK th tc o Combinatorial Output REGISTERED OUTPUT 1/ fm a x (external fdbk) Registered Output INPUT or I/O FEEDBACK tdis OUTPUT ten CLK 1/ fm a x (int ern al fd bk ) Input or I/O to Output Enable/Disable REGISTERED FEEDBACK tc f tsu fmax with Feedback tw h CLK 1/ tw l fm a x (w/o fdbk) Clock Width INPUT or I/O FEEDBACK DRIVING SP CLK INPUT or I/O FEEDB ACK DRIVI NG AR tsu th tspr CLK tarw tco REGISTERED OUTPUT R E G I S T ER E D OUTPUT tarr tar Synchronous Preset Asynchronous Reset 8 Specifications GAL26CLV12 fmax Descriptions CLK LOGIC ARRAY REGISTER CLK LOGIC ARRAY tsu tco REGISTER fmax with External Feedback 1/(tsu+tco) Note: fmax with external feedback is calculated from measured tsu and tco. CLK tcf tpd LOGIC ARRAY fmax with Internal Feedback 1/(tsu+tcf) REGISTER tsu + th fmax with No Feedback Note: fmax with no feedback may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combinatorial output is equal to tcf + tpd. Switching Test Conditions Input Pulse Levels Input Rise and Fall Times Input Timing Reference Levels Output Timing Reference Levels Output Load Output Load Conditions (see figure) Test Condition A B C High Z to Active High at 1.9V High Z to Active Low at 1.0V Active High to High Z at 1.9V Active Low to High Z at 1.0V R1 50 50 50 50 50 CL 35pF 35pF 35pF 35pF 35pF GND to 3.0V 1.5ns 10% - 90% 1.5V 1.5V See Figure FROM OUTPUT (O/Q) UNDER TEST Z0 = 50, CL = 35pF* TEST POINT R1 +1.45V *CL includes test fixture and probe capacitance. 9 Specifications GAL26CLV12 Electronic Signature An electronic signature (ES) is provided in every GAL26CLV12D device. It contains 64 bits of reprogrammable memory that can contain user-defined data. Some uses include user ID codes, revision numbers, or inventory control. The signature data is always available to the user independent of the state of the security cell. Output Register Preload When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. This is because certain events may occur during system operation that throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc.). To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. Then the machine can be sequenced and the outputs tested for correct next state conditions. The GAL26CLV12D device includes circuitry that allows each registered output to be synchronously set either high or low. Thus, any present state condition can be forced for test sequencing. If necessary, approved GAL programmers capable of executing test vectors perform output register preload automatically. Security Cell A security cell is provided in every GAL26CLV12D device to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device. This cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed. The Electronic Signature is always available to the user, regardless of the state of this control cell. Latch-Up Protection GAL26CLV12D devices are designed with an on-board charge pump to negatively bias the substrate. The negative bias is of sufficient magnitude to prevent input undershoots from causing the circuitry to latch. Input Buffers GAL26CLV12D devices are designed with TTL level compatible input buffers. These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices. The input and I/O pins on the GAL26CLV12D also have built-in active pull-ups. As a result, floating inputs will float to a TTL high (logic 1). However, Lattice Semiconductor recommends that all unused inputs and tri-stated I/O pins be connected to an adjacent active input, Vcc, or ground. Doing so will tend to improve noise immunity and reduce Icc for the device. (See equivalent input and I/O schematics on the following page.) Typical Input Pull-up Characteristic 0 -10 Input Current (A) Device Programming GAL devices are programmed using a Lattice Semiconductorapproved Logic Programmer, available from a number of manufacturers (see the the GAL Development Tools section). Complete programming of the device takes only a few seconds. Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle. -20 -30 -40 -50 -60 -70 -80 0 1 2 3 0.5 1.5 2.5 3.5 4 Input Voltage (V) 10 Specifications GAL26CLV12 Power-Up Reset Vcc (min.) Vcc tsu CLK twl tpr INTERNAL REGISTER Q - OUTPUT Internal Register Reset to Logic "0" ACTIVE LOW OUTPUT REGISTER Device Pin Reset to Logic "1" ACTIVE HIGH OUTPUT REGISTER Device Pin Reset to Logic "0" Circuitry within the GAL26CLV12D provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, 1s MAX). As a result, the state on the registered output pins (if they are enabled) will be either high or low on power-up, depending on the programmed polarity of the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. The timing diagram for power-up is shown below. Because of the asyn- chronous nature of system power-up, some conditions must be met to provide a valid power-up reset of the GAL26CLV12D. First, the Vcc rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. The registers will reset within a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock must also meet the minimum pulse width requirements. Input/Output Equivalent Schematics PIN Feedback PIN Vcc Active Pull-up Circuit Active Pull-up Circuit Tri-State Control Vcc Vref Vcc ESD Protection Circuit Vref Vcc PIN Data Output PIN ESD Protection Circuit Typ. Vref = Vcc Typical Input Typ. Vref = Vcc Feedback (To Input Buffer) Typical Output 11 Specifications GAL26CLV12 GAL26CLV12D: Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.1 1.1 Normalized Tco vs Vcc 1.2 Normalized Tsu vs Vcc Normalized Tpd 1.05 Normalized Tco Normalized Tsu RISE FALL 1.05 RISE FALL 1.1 RISE FALL 1 1 1 0.95 0.95 0.9 0.9 3 3.15 3.3 3.45 3.6 0.9 3 3.15 3.3 3.45 3.6 0.8 3 3.15 3.3 3.45 3.6 Supply Voltage (V) Supply Voltage (V) Supply Voltage (V) Normalized Tpd vs Temp 1.3 1.2 Normalized Tco vs Temp 1.3 Normalized Tsu vs Temp Normalized Tpd Normalized Tco 1.2 1.1 1.1 Normalized Tsu RISE FALL RISE FALL 1.2 RISE FALL 1.1 1 1 1 0.9 0.9 0.8 -55 -25 0 25 50 75 100 125 0.9 -55 -25 0 25 50 75 100 125 0.8 -55 -25 0 25 50 75 1 00 1 25 Temperature (deg. C) Temperature (deg. C) Temperature (deg. C) Delta Tpd vs # of Outputs Switching 0 0 Delta Tco vs # of Outputs Switching Delta Tpd (ns) Delta Tco (ns) -0.1 -0.1 -0.2 -0.2 -0.3 RISE FALL -0.3 RISE FALL -0.4 -0.4 1 2 3 4 5 6 7 8 9 10 11 1 2 -0.5 1 2 3 4 5 6 7 8 9 10 11 1 2 Number of Outputs Switching Delta Tpd vs Output Loading 20 16 20 Number of Outputs Switching Delta Tco vs Output Loading Delta Tpd (ns) 12 8 4 0 -4 -8 0 50 Delta Tco (ns) RISE FALL 16 12 8 4 0 -4 RISE FALL 100 150 200 250 3 00 0 50 100 150 200 250 3 00 Output Loading (pF) Output Loading (pF) 12 Specifications GAL26CLV12 GAL26CLV12D: Typical AC and DC Characteristic Diagrams Vol vs Iol 1 3 Voh vs Ioh 3 Voh vs Ioh 0.8 2.5 Voh (V) 0.6 2 0.4 Voh (V) 0 5 10 15 20 25 2.9 Vol (V) 2.8 0.2 1.5 0 0 5 10 15 20 25 30 1 2.7 0.00 1.00 2.00 3.00 4.00 5.00 Iol (mA) Normalized Icc vs Vcc 1.2 1.3 Ioh(mA) Normalized Icc vs Temp 1.35 1.3 Ioh(mA) Normalized Icc vs Freq Normalized Icc Normalized Icc 1.1 Normalized Icc -25 0 25 50 88 100 125 1.2 1.25 1.2 1.15 1.1 1.05 1.1 1 1 0.9 0.9 0.8 3 3.15 3.3 3.45 3.6 0.8 -55 1 1 15 25 50 75 1 00 Supply Voltage (V) Temperature (deg. C) Frequency (MHz) Delta Icc vs Vin (1 input) 9 8 0 10 20 30 40 50 1 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 60 -4 -3.5 Input Clamp (Vik) Delta Icc (mA) 7 5 4 3 2 Iik (mA) 6 -3 -2.5 -2 -1.5 -1 -0.5 0 Vin (V) Vik (V) 13 |
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